Conventionally, an off-chip output capacitor is required for achieving low-dropout regulator (LDO) stability, as well as good line and load regulations. However, the off-chip capacitor is the main obstacle to fully integrating the LDO in system-on-chip (SoC) applications. With the recent rapid development of SoC designs, there is a growing trend towards the integration of integrated circuits systems and power-management circuits. Local, on-chip and capacitor-free LDO regulators are important for future SoC applications. The capacitor-free feature significantly reduces system cost and board space, and also simplifies system design since external off-chip capacitor is eliminated.
Generally, for high-precision applications, a high low-frequency gain of the LDO regulators is required. A particular problem is that as the power supply voltage is scaled down in the current trends, the threshold voltage is not necessarily scaled down in the same way. At low supply voltages, cascade topology is no longer suitable for achieving high low-frequency gain. Instead, multi-stage approach is widely used by cascading several stages horizontally. However, the stability and the bandwidth of the LDO regulators with cascaded approach are both limited by the existing frequency compensation techniques. Currently, due to the stability issue, state-of-the-art capacitor-free LDO regulators need a minimum load current, typically around 10 mA, to be stable under normal operation. However, this minimum load current requirement is a major obstacle to applying capacitor-free LDO regulators in system-on-chip applications.